The present invention relates generally to integrated circuits, and relates more particularly to high-performance band-edge complementary metal-oxide-semiconductor technology.
Complementary metal-oxide-semiconductor (CMOS) is a major class of integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static random access memory (RAM), and other digital logic circuits. To meet performance requirements for 32 nm and beyond technology nodes, manufacturers have proposed replacing conventional polysilicon gate electrodes with high-K dielectric materials and replacing conventional silicon dioxide-based gate dielectrics with metal gate materials. In addition, capping material on the high-K dielectric gate electrode, on the metal gate dielectric, or on the gate electrode material has been proposed to lower the threshold voltage (Vt) of the transistor for better short channel effect.
Most attempts to fabricate such CMOS devices with the capping, however, have produced undesirable effects. For instance, although band-edge n-type metal-oxide-semiconductor field effect transistors (BE nMOSFETs) have been successfully produced by capping the high-K dielectric gate electrode through conventional gate first processing, the high-temperature annealing process results in interfacial oxide growth and flatband voltage (Vfb)/threshold voltage (Vt) instability in BE p-type metal-oxide-semiconductor (BE pMOSFETs). At lower temperatures, however, planarization of the two different n-type and p-type materials has proven challenging, and re-deposition of the high-K dielectric gate electrode material has resulted in detrimental parasitic capacitance.
Thus, there is a need in the art for a method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device.